The following reference provide some information about the state of the art:    [1] K. N. ManjulaRani, et al., “Hot-carrier reliability study and simulation methodology development for 65 nm technology”, IEEE International Integrated Reliability Workshop Final Reports, pp. 124-127, 2009.    [2] J. Kim, et al., “A Linear Multi-Mode CMOS Power Amplifier with Discrete Resizing and Concurrent Power Combining Structure”, ISSCC, Vol. 46, No. 5, May 2011.    [3] S. Kang, et al., “A 5-GHz WiFi RF CMOS Power Amplifier with a Parallel-Cascoded Configuration and an Active Feedback Linearize”, IEEE Transactions on Microwave Theory and Techniques, Vol. 65, pp. 3230-3244, April 2017.    [4] W. Ye, et al., “A 2-to-6 GHz Class-AB Power Amplifier with 28.4% PAE in 65 nm CMOS Supporting 256QAM”, ISSCC, pp. 38-40, April 2015.    [5] J. Park, et al., “A CMOS Antiphase Power Amplifier With an MGTR Technique for Mobile Applications”, IEEE Transactions on Microwave Theory and Techniques, Vol. 65, No. 11, pp. 4645-4656, 2017.    [6] V. Camarchia, et al., “The Doherty power amplifier: Review of recent solutions and trends”, IEEE Transactions on Microwave Theory and Techniques, Vol. 63, No. 2, pp. 559-571, 2015    [7] S. Modi, et al., “Efficiency improvement of Doherty power amplifiers using supply switching and gate bias modulation.” 2014 IEEE 15th Annual Wireless and
FIG. 1 is a graph 10 that illustrates the relationships between output power, bandwidth (BW), EVM and PAE of various prior art power amplifiers such as PCT, PCC, MGTR, Doherty and switching mode.
In the recent decade there has been a strong demand to use CMOS technologies when implementing RF power amplifiers as part of a transceiver or a front-end module for the IEEE 802.11ac/ax WiFi standards. However, CMOS technologies are notorious for their poor linearity and inadequate protection from voltage and current stresses [1], which usually cause reliability and breakdown problems for WiFi access points where the PA is supplied by 3 to 5V.
In addition to minimization of the PA's power consumption, it is also desirable to achieve high efficiency at power back-off (PBO) in it, while keeping low levels of AM-AM and AM-PM distortions for a targeted EVM performance of −35 dB, preferably without digital pre-distortion (DPD) mechanisms of high-complexity.
There are several well-known approaches to address this in order to design highly-efficient, highly-linear CMOS PAs, while avoiding voltage and current stress in the CMOS transistors. The cascode transistor configuration is widely used in order to reduce the voltage stress over the CMOS transistors. However, it is also very important to reduce the current density in the transistors.
Using switching mode power amplifiers or highly efficient topologies, such as Doherty, allows the PA to reach high PAE in the deep PBO region, as shown in FIG. 1.
However, these solutions require a DPD engine, phase shifters and programmable higher-Q resonant tank circuits to correct for the PA nonlinearity over the targeted output power and operating frequency ranges.
Techniques such as parallel-combining transformer (PCT) [2], parallel-cascoded configuration (PCC) with active feedback linearizer [3] and multigate transistor (MGTR) [5], can all improve the linearity of the PA, but will increase its power consumption when achieving the targeted EVM performance of −35 dB because the cascode transistors are connected to the same load.
A combination of the above techniques allows us to achieve enhanced performance of the RF power amplifier. However, the disadvantages of the combination are the complexity of the algorithms and calibration tests; reduced output power; increased size of the hardware or increased power consumption due to the additional look-up table.
Therefore, a new PA topology is needed, which would allow us to control and improve all the important parameters at once, such as bandwidth, output power, efficiency and EVM.